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19-2736; Rev 0; 1/03
14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range
General Description
The MAX1156/MAX1158/MAX1174 14-bit, low-power, successive-approximation analog-to-digital converters (ADCs) feature automatic power-down, a factorytrimmed internal clock, and a byte-wide parallel interface. The devices operate from a single +4.75V to +5.25V analog supply and feature a separate digital supply input for direct interface with +2.7V to +5.25V digital logic. The MAX1156 accepts a 0 to +10V analog input voltage range. The MAX1158 accepts a 10V bipolar analog input voltage range, while the MAX1174 accepts a 5V bipolar analog input voltage range. All devices consume no more than 26.5mW at a sampling rate of 135ksps when using an external reference, and 31mW when using the internal +4.096V reference. AutoShutdownTM reduces supply current to 0.4mA (typ) at 10ksps. The MAX1156/MAX1158/MAX1174 are ideal for highperformance, battery-powered, data-acquisition applications. Excellent AC performance (THD = -100dB) and DC accuracy (1LSB INL) make the MAX1156/ MAX1158/MAX1174 ideal for industrial process control, instrumentation, and medical applications. The MAX1156/MAX1158/MAX1174 are available in a 20-pin TSSOP package and are fully specified over the -40C to +85C extended temperature range and the 0C to +70C commercial temperature range. o Byte-Wide Parallel Interface o Analog Input Voltage Range: 10V, 5V, 0 to 10V o Single +4.75V to +5.25V Analog Supply Voltage o Interface with +2.7V to +5.25V Digital Logic o 1LSB INL (max) o 1LSB DNL (max) o Low Supply Current (max) 2.9mA (External Reference) 3.8mA (Internal Reference) 5A AutoShutdown Mode o Small Footprint o 20-Pin TSSOP Package
Features
MAX1156/MAX1158/MAX1174
Ordering Information
PART MAX1156ACUP MAX1156BCUP MAX1156AEUP MAX1156BEUP TEMP RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C INPUT PINVOLTAGE PACKAGE RANGE 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 0 to +10V 0 to +10V 0 to +10V 0 to +10V
Ordering Information continued at end of data sheet.
Applications
Temperature Sensing and Monitoring Industrial Process Control I/O Modules Data-Acquisition Systems Precision Instrumentation
ANALOG INPUT
Typical Operating Circuit
+5V ANALOG 0.1F +5V DIGITAL 0.1F
AVDD AIN
DVDD
P DATA D0-D7 BUS OR D8-D13 EOC REF REFADJ
R/C CS HBEN HIGH BYTE LOW BYTE
MAX1156 MAX1158 MAX1174
Pin Configuration appears at end of data sheet.
AGND DGND
0.1F
10F
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AIN to AGND .....................................................-16.5V to +16.5V REF, REFADJ to AGND............................-0.3V to (AVDD + 0.3V) CS, R/C, HBEN to DGND .........................................-0.3V to +6V D_, EOC to DGND ...................................-0.3V to (DVDD + 0.3V) Maximum Continuous Current into any Pin.........................50mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 10.9mW/C above +70C) .......879mW Operating Temperature Range MAX11_ _ _CUP..................................................0C to +70C MAX11_ _ _EUP ...............................................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V 5%, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Transition Noise Offset Error Gain Error Offset Drift Gain Drift AC ACCURACY (fIN = 1kHz, VAIN = full range, 135ksps) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range ANALOG INPUT MAX1156 Input Range VAIN MAX1158 MAX1174 MAX1156/MAX1174 MAX1156 Input Resistance RAIN MAX1174 MAX1158 Normal operation Shutdown mode Shutdown mode Normal operation Shutdown mode 0 -10 -5 5.3 5.3 3.0 7.8 6.0 10 13.0 k 6.9 +10 +10 +5 9.2 V SINAD SNR THD SFDR 87 81 82 85 85 -100 103 -86 dB dB dB dB RES DNL INL No missing codes over temperature MAX11_ _A MAX11_ _B RMS noise, external reference Internal reference -10 14 -1 -1 -2 0.32 0.34 0 0 16 1 +10 0.2 +1 +1 +2 Bits LSB LSB LSBRMS mV %FSR V/C ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V 5%, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MAX1156, 0 VAIN +10V Input Current IAIN MAX1158, -10V VAIN +10V MAX1174, -5V VAIN +5V Normal operation Shutdown mode Normal operation Shutdown mode MIN -0.1 -1.8 -1.8 -1.8 -1.8 0.5 1 10 4.056 4.096 35 IREF-SC 10 4.136 TYP MAX +2.0 +1.2 +1.8 +0.4 +1.8 0.7 mA MAX1174, VAIN = +5V, shutdown mode to operating mode 1.4 pF V ppm/C mA mA UNITS
MAX1156/MAX1158/MAX1174
MAX1158, VAIN = +10V, shutdown mode to operating mode Input Current Step at Power-Up IPU
Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Output Tempco REF Short-Circuit Current EXTERNAL REFERENCE REF and REFADJ Input Voltage Range REFADJ Buffer Disable Threshold REF Input Current REFADJ Input Current DIGITAL INPUTS/OUTPUTS Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance Three-State Output Leakage Three-State Output Capacitance
CIN VREF
3.8 AVDD 0.4 IREF IREFADJ Normal mode, fSAMPLE = 135ksps Shutdown mode (Note 1) REFADJ = AVDD ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V ISINK = 1.6mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V 0.7 x DVDD DVDD 0.4 60 0.1 16
4.2 AVDD 0.1 100 10
V V A A
VOH VOL VIH VIL
V 0.4 V V 0.3 x DVDD V A V pF 10 15 A pF
Digital input = DVDD or 0V VHYST CIN IOZ COZ
-1 0.2 15
+1
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V 5%, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER POWER SUPPLIES Analog Supply Voltage Digital Supply Voltage AVDD DVDD External reference, 135ksps Analog Supply Current IAVDD Internal reference, 135ksps MAX1156 MAX1158/MAX1174 MAX1156 MAX1158/MAX1174 5.2 0.5 3.7 0.75 AVDD = DVDD = +4.75V to +5.25V 1 4 4.75 2.70 5.25 5.25 2.9 5.3 3.8 6.2 5 A mA mA LSB mA V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Shutdown Supply Current Digital Supply Current Power-Supply Rejection
ISHDN IDVDD
Shutdown mode (Note 1), digital input = DVDD or 0V Standby mode
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V 5%, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to TMAX.)
PARAMETER Maximum Sampling Rate Acquisition Time Conversion Time CS Pulse Width High CS Pulse Width Low R/C to CS Fall Setup Time R/C to CS Fall Hold Time CS to Output Data Valid EOC Fall to CS Fall CS Rise to EOC Rise Bus Relinquish Time HBEN Transition to Output Data Valid SYMBOL fSAMPLE-MAX tACQ tCONV tCSH tCSL tDS tDH tDO tDV tEOC tBR tDO1 DVDD = +4.75V to +5.25V DVDD = +2.7V to +5.25V DVDD = +4.75V to +5.25V DVDD = +2.7V to +5.25V DVDD = +4.75V to +5.25V DVDD = +2.7V to +5.25V DVDD = +4.75V to +5.25V DVDD = +2.7V to +5.25V DVDD = +4.75V to +5.25V DVDD = +2.7V to +5.25V 0 40 80 40 80 40 80 (Note 2) (Note 2) DVDD = +4.75V to +5.25V DVDD = +2.7V to +5.25V 40 40 60 0 40 60 40 80 2 4.7 CONDITIONS MIN TYP MAX 135 UNITS ksps s s ns ns ns ns ns ns ns ns ns
Note 1: Maximum specification is limited by automated test equipment. Note 2: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range
Typical Operating Characteristics
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Typical Application Circuit)
INL vs. CODE
2.5 2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE DNL (LSB)
MAX1156/58/74 toc01
MAX1156/MAX1158/MAX1174
DNL vs. CODE
1.0 0.8 0.6 SUPPLY CURRENT (mA) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE 4.70 4.65 4.60 4.55
MAX1156/58/74 toc02
SUPPLY CURRENT (AVDD + DVDD) vs. TEMPERATURE
4.75 5.0V 5.25V
MAX1156/58/74 toc03
4.80
4.75V 4.50 4.45 4.40 -40 -20 0 20 40 60 80 TEMPERATURE (C) fSAMPLE = 135ksps SHUTDOWN MODE BETWEEN CONVERSIONS
SUPPLY CURRENT (AVDD + DVDD) vs. SAMPLE RATE
MAX1156/58/74 toc04
SHUTDOWN CURRENT (AVDD + DVDD) vs. TEMPERATURE
MAX1156/58/74 toc05
OFFSET ERROR vs. TEMPERATURE
8 6 OFFSET ERROR (mV) 4 2 0 -2 -4 -6 -8 -10 MAX1156 MAX1158 MAX1174
MAX1156/58/74 toc06
10 STANDBY MODE
5.0 SHUTDOWN SUPPLY CURRENT (A) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20
NO CONVERSIONS
10
1 SUPPLY CURRENT (mA)
0.1 SHUTDOWN MODE
0.01
0.001 VAIN = 0V 0.0001 0.01 0.1 1 10 100 1000 SAMPLE RATE (ksps)
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE
MAX1156/58/74 toc07
INTERNAL REFERENCE vs. TEMPERATURE
MAX1156/58/74 toc08
FFT AT 1kHz
-20 -40 MAGNITUDE (dB) -60 -80 -100 -120 -140 -160 -180 fSAMPLE = 131ksps
MAX1156/58/74 toc09
0.20 0.15 GAIN ERROR (%FSR) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -40 -20 0 20 40 60 80 TEMPERATURE (C)
4.136 4.126 INTERNAL REFERENCE (V) 4.116 4.106 4.096 4.086 4.076 4.066 4.056 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0
0
10
20
30
40
50
60
FREQUENCY (kHz)
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10F, CREFADJ = 0.1F, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Typical Application Circuit)
SINAD vs. FREQUENCY
MAX1156/58/74 toc10
SFDR vs. FREQUENCY
MAX1156/58/74 toc11
THD vs. FREQUENCY
-10 -20 -30 THD (dB) -40 -50 -60 -70 -80 -90
MAX1156/58/74 toc12
100 90 80 70 SINAD (dB) 60 50 40 30 20 10 0 1 10 FREQUENCY (kHz) fSAMPLE = 131ksps
120 100 80 SFDR (dB) 60 40 20 fSAMPLE = 131ksps 0 1 10 FREQUENCY (kHz)
0
-100 -110 100 1 10
fSAMPLE = 131ksps 100
100
FREQUENCY (kHz)
Pin Description
PIN 1 2 3 4 NAME D4/D12 D5/D13 D6/0 D7/0 Three-State Digital Data Output Three-State Digital Data Output. D13 is the MSB. Three-State Digital Data Output Three-State Digital Data Output Read/Convert Input. Power up and put the MAX1156/MAX1158/MAX1174 in acquisition mode by holding R/C low during the first falling edge of CS. During the second falling edge of CS, the level on R/C determines whether the reference and reference buffer power down or remain on after conversion. Set R/C high during the second falling edge of CS to power down the reference and buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third falling edge of CS to put valid data on the bus. End of Conversion. EOC drives low when conversion is complete. Analog Supply Input. Bypass with a 0.1F capacitor to AGND. Analog Ground. Primary analog ground (star ground). Analog Input Analog Ground. Connect pin 10 to pin 8. Reference Buffer Output. Bypass REFADJ with a 0.1F capacitor to AGND for internal reference mode. Connect REFADJ to AVDD to select external reference mode. Reference Input/Output. Bypass REF with a 10F capacitor to AGND for internal reference mode. External reference input when in external reference mode. FUNCTION
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R/C
6 7 8 9 10 11 12
EOC AVDD AGND AIN AGND REFADJ REF
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range
Pin Description (continued)
PIN 13 NAME HBEN FUNCTION High-Byte Enable Input. Used to multiplex the 14-bit conversion result. 1: Most significant byte available on the data bus. 0: Least significant byte available on the data bus. Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result onto the bus when R/C is high. Digital Ground Digital Supply Voltage. Bypass with a 0.1F capacitor to DGND. Three-State Digital Data Output. D0 is the LSB. Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output
MAX1156/MAX1158/MAX1174
14 15 16 17 18 19 20
CS DGND DVDD D0/D8 D1/D9 D2/D10 D3/D11
DVDD 1mA
DO-D13 DO-D13
Analog Input
Input Scaler The MAX1156/MAX1158/MAX1174 have an input scaler, which allows conversion of true bipolar input voltages and input voltages greater than the power supply, while operating from a single +5V analog supply. The input scaler attenuates and shifts the analog input to match the input range of the internal DAC. The MAX1156 has a unipolar input voltage range of 0 to +10V. The MAX1158 input voltage range is 10V while the MAX1174 input voltage range is 5V. Figure 4 shows the equivalent input circuit of the MAX1156/ MAX1158/MAX1174. This circuit limits the current going into or out of AIN to less than 1.8mA. Track and Hold (T/H) In track mode, the internal hold capacitor acquires the analog signal (see Figure 4). In hold mode, the T/H switches open and the capacitive DAC samples the analog input. During the acquisition, the analog input (AIN) charges capacitor CHOLD. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on CHOLD represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion time to restore node T/H OUT to zero within the limits of 14-bit resolution. Force CS low to put valid data on the bus after conversion is complete.
1mA DGND
CLOAD = 20pF
CLOAD = 20pF DGND b) HIGH-Z TO VOL, VOH TO VOL, AND VOL TO HIGH-Z
a) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z
Figure 1. Load Circuits
Detailed Description
Converter Operation
The MAX1156/MAX1158/MAX1174 use a successiveapproximation (SAR) conversion technique with an inherent track-and-hold (T/H) stage to convert an analog input into a 14-bit digital output. Parallel outputs provide a high-speed interface to microprocessors (Ps). The Functional Diagram shows a simplified internal architecture of the MAX1156/MAX1158/MAX1174. Figure 3 shows a typical application circuit for the MAX1156/MAX1158/MAX1174.
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
tCSL CS tACQ R/C tDH EOC tCONV tDO REF POWERDOWN CONTROL tDS tDV tEOC tCSH
HBEN HIGH-Z D7/D15-D0/D8 tDO tDO1 HIGH/LOW BYTE VALID tBR HIGH-Z HIGH/LOW BYTE VALID
Figure 2. MAX1156/MAX1158/MAX1174 Timing Diagram
Power-Down Modes
Select standby mode or shutdown mode with the R/C bit during the second falling edge of CS (see the Selecting Standby or Shutdown Mode section). The MAX1156/MAX1158/MAX1174 automatically enter either standby mode (reference and buffer on) or shutdown (reference and buffer off) after each conversion, depending on the status of R/C during the second falling edge of CS.
+5V ANALOG +5V DIGITAL
0.1F
0.1F
AVDD
DVDD P DATA D0-D7 BUS OR D8-D13 MAX1156 MAX1158 MAX1174 EOC REF REFADJ AGND DGND 0.1F 10F
Internal Clock
The MAX1156/MAX1158/MAX1174 generate an internal conversion clock to free the microprocessor from the burden of running the SAR conversion clock. Total conversion time (tCONV) after entering hold mode (second falling edge of CS) to end of conversion (EOC) falling is 4.7s (max).
ANALOG INPUT
AIN
R/C CS HBEN HIGH BYTE LOW BYTE
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the MAX1156/MAX1158/MAX1174 (see Figure 2). The first falling edge of CS powers up the device and puts it in acquire mode if R/C is low. The convert start is ignored if R/C is high. The MAX1156/MAX1158/MAX1174 need at least 12ms (CREFADJ = 0.1F, CREF = 10F) for the internal reference to wake up and settle before starting the conversion, if powering up from shutdown.
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Figure 3. Typical Application Circuit for the MAX1156/MAX1158/ MAX1174
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
REF MAX1156 R2 AIN R3 161 R1 3.4k TRACK S1 HOLD TRACK HOLD S2 CHOLD 30pF T/H OUT R3 S3 POWERDOWN R2 = 7.85k (MAX1158) OR 3.92k (MAX1156/MAX1174) S1, S2 = T/H SWITCH S3 = POWER-DOWN (MAX1158/MAX1174 ONLY) R3 = 5.45k (MAX1158) OR 17.79k (MAX1156/MAX1174) HOLD TRACK HOLD S2 MAX1158/MAX1174 R2 AIN 161 R1 3.4k TRACK S1 CHOLD 30pF T/H OUT
Figure 4. Equivalent Input Circuit
Selecting Standby or Shutdown Mode
The MAX1156/MAX1158/MAX1174 have a selectable standby or low-power shutdown mode. In standby mode, the ADC's internal reference and reference buffer do not power down between conversions, eliminating the need to wait for the reference to power up before performing the next conversion. Shutdown mode powers down the reference and reference buffer after completing a conversion. The reference and reference buffer require a minimum of 12ms (CREFADJ = 0.1F, CREF = 10F) to power up and settle from shutdown. The state of R/C at the second falling edge of CS selects which power-down mode the MAX1156/ MAX1158/MAX1174 enter upon conversion completion. Holding R/C low causes the MAX1156/MAX1158/ MAX1174 to enter standby mode. The reference and buffer are left on after the conversion completes. R/C high causes the MAX1156/MAX1158/MAX1174 to enter shutdown mode and power down the reference and buffer after conversion (see Figures 5 and 6). Set the voltage at R/C high during the second falling edge of CS to realize the lowest current operation.
Standby Mode While in standby mode, the supply current is less than 3.7mA (typ). The next falling edge of CS with R/C low causes the MAX1156/MAX1158/MAX1174 to exit standby mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time. Shutdown Mode In shutdown mode, the reference and reference buffer are shut down between conversions. Shutdown mode reduces supply current to 0.5A (typ) immediately after the conversion. The next falling edge of CS with R/C low causes the reference and buffer to wake up and enter acquisition mode. To achieve 14-bit accuracy, allow 12ms (CREFADJ = 0.1F, CREF = 10F) for the internal reference to wake up.
Internal and External Reference
Internal Reference The internal reference of the MAX1156/MAX1158/ MAX1174 is internally buffered to provide +4.096V output at REF. Bypass REF to AGND and REFADJ to AGND with 10F and 0.1F, respectively. Sink or source current at REFADJ to make fine adjustments to the internal reference. The input impedance of REFADJ is nominally 5k. Use the circuit of Figure 7 to adjust the internal reference to 1.5%.
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
ACQUISITION CONVERSION DATA OUT ACQUISITION CONVERSION DATA OUT
CS
CS
R/C
R/C
EOC REF AND BUFFER POWER
EOC REF AND BUFFER POWER
Figure 5. Selecting Standby Mode
Figure 6. Selecting Shutdown Mode
External Reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the MAX1156/ MAX1158/MAX1174's internal buffer amplifier. Using the buffered REFADJ input makes buffering the external reference unnecessary. The input impedance of REFADJ is typically 5k. The internal buffer output must be bypassed at REF with a 10F capacitor. Connect REFADJ to AVDD to disable the internal buffer. Directly drive REF using an external 3.8V to 4.2V reference. During conversion, the external reference must be able to drive 100A of DC load current and have an output impedance of 10 or less. For optimal performance, buffer the reference through an op amp and bypass REF with a 10F capacitor. Consider the MAX1156/MAX1158/MAX1174's equivalent input noise (0.32LSB) when choosing a reference.
HBEN toggles the output between the high/low byte. The low byte is loaded onto the output bus when HBEN is low and the high byte is on the bus when HBEN is high. The two MSBs of the high byte are always zero.
Transfer Function
Figures 8, 9, and 10 show the MAX1156/MAX1158/ MAX1174 output transfer functions. The MAX1158 and MAX1174 outputs are coded in offset binary, while the MAX1156 is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to achieve 14-bit accuracy and prevent loading the source. Switch the channels immediately after acquisition, rather than near the end of or after a conversion, when the input signal is multiplexed. This allows more time for the input buffer amplifier to respond to a large step-change in input signal. The input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. Figure 11 shows an example of this circuit using the MAX427. Figures 12a and 12b show how the MAX1158 and MAX1174 analog input current varies depending on whether the chip is operating or powered down. The part is fully powered down between conversions if the voltage at R/C is set high during the second falling edge of CS. The input current abruptly steps to the powered up value at the start of acquisition. This step in the input current can disrupt the ADC input, depending on the driving circuit's output impedance at high frequencies. If the driving circuit cannot fully settle by
Reading the Conversion Result
EOC is provided to flag the microprocessor when a conversion is complete. The falling edge of EOC signals that the data is valid and ready to be output to the bus. D0-D13 are the parallel outputs of the MAX1156/MAX1158/MAX1174. These three-state outputs allow for direct connection to a microcontroller I/O bus. The outputs remain high-impedance during acquisition and conversion. Data is loaded onto the output bus with the third falling edge of CS with R/C high (after tDO). Bringing CS high forces the output bus back to high impedance. The MAX1156/MAX1158/MAX1174 then wait for the next falling edge of CS to start the next conversion cycle (see Figure 2).
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
OUTPUT CODE 11 1111 1111 1111 MAX1156 INPUT RANGE = 0 TO +10V FULL-SCALE TRANSITION
+5V 68k 100k
MAX1156 MAX1158 MAX1174
REFADJ
11 1111 1111 1110 11 1111 1111 1101
FULL-SCALE RANGE (FSR) = +10V 00 0000 0000 0011 00 0000 0000 0010 00 0000 0000 0001 00 0000 0000 0000 0 1 2 3 INPUT VOLTAGE (LSB) 16383 16382 16384 1LSB = FSR x VREF 16384 x 4.096
150k
0.1F
Figure 7. MAX1156/MAX1158/MAX1174 Reference Adjust Circuit
Figure 8. MAX1156 Transfer Function
OUTPUT CODE 11 1111 1111 1111 11 1111 1111 1110 11 1111 1111 1101 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0011 00 0000 0000 0010 00 0000 0000 0001
MAX1158 INPUT RANGE = -10V TO +10V FULL-SCALE TRANSITION
OUTPUT CODE 11 1111 1111 1111 11 1111 1111 1110 11 1111 1111 1101 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0011 00 0000 0000 0010 00 0000 0000 0001
MAX1174 INPUT RANGE = -5V TO +5V FULL-SCALE TRANSITION
FULL-SCALE RANGE (FSR) = +20V 1LSB = FSR x VREF 16384 x 4.096
FULL-SCALE RANGE (FSR) = +10V 1LSB = FSR x VREF 16384 x 4.096
00 0000 0000 0000 0 +8190 +8192 -8192 -8190 -1 +1 -8191 -8189 +8191 INPUT VOLTAGE (LSB)
00 0000 0000 0000 0 +8190 +8192 -8192 -8190 -1 +1 -8191 -8189 +8191 INPUT VOLTAGE (LSB)
Figure 9. MAX1158 Transfer Function
Figure 10. MAX1174 Transfer Function
the end of acquisition, the accuracy of the system can be compromised. To avoid this situation, increase the acquisition time, use a driving circuit that can settle within tACQ, or leave the MAX1158/MAX1174 powered up by setting the voltage at R/C low during the second falling edge of CS.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do not run analog and digital lines parallel to each other, and do not layout digital signal paths underneath the
ADC package. Use separate analog and digital ground planes with only one point connecting the two ground systems (analog and digital) as close to the device as possible. Route digital signals far away from sensitive analog and reference inputs. If digital lines must cross analog lines, do so at right angles to minimize coupling digital noise onto the analog lines. If the analog and digital sections share the same supply, isolate the digital and analog
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11
14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
MAX1174 ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE
1.5 ** ANALOG INPUT CURRENT (mA) 1.0 0.5 0 -0.5 -1.0 -1.5 -5.0 -2.5 0 2.5 5.0 ANALOG INPUT VOLTAGE (V) STANDBY MODE SHUTDOWN MODE
REF MAX1156 MAX1158 MAX1174 ANALOG INPUT
MAX427
* AIN
*MAX1156 ONLY. **MAX1158/MAX1174 ONLY.
Figure 11. MAX1156/MAX1158/MAX1174 Fast-Settling Input Buffer
Figure 12a. MAX1174 Analog Input Current
supply by connecting them with a low value (10) resistor or ferrite bead. The ADC is sensitive to high-frequency noise on the AV DD supply. Bypass AV DD to AGND with a 0.1F capacitor in parallel with a 1F to 10F low-ESR capacitor with the smallest capacitor closest to the device. Keep capacitor leads short to minimize stray inductance.
MAX1158 ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE
1.5 ANALOG INPUT CURRENT (mA) 1.0 0.5 0 -0.5 -1.0 -1.5 -10 -5 0 5 10 ANALOG INPUT VOLTAGE (V) STANDBY MODE SHUTDOWN MODE
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1156/MAX1158/ MAX1174 are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of 1LSB guarantees no missing codes and a monotonic transfer function.
Figure 12b. MAX1158 Analog Input Current
12
______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76) dB where N = 14 bits. In reality, there are other noise sources besides quantization noise; thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. zation noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = SINAD -1.76 6.02
MAX1156/MAX1158/MAX1174
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 THD = 20 x log V1
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals. SignalRMS SINAD(dB) = 20 x log (Noise + Distortion)RMS
where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest frequency component.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quanti-
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13
14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1156/MAX1158/MAX1174
Functional Diagram
REFADJ 5k REFERENCE 8 BITS 8 BITS D0-D7 OR D8-D13 HBEN AVDD AGND DVDD DGND
OUTPUT REGISTERS REF
AIN
INPUT SCALER
CAPACITIVE DAC
AGND SUCCESSIVEAPPROXIMATION REGISTER AND CONTROL LOGIC
MAX1156 MAX1158 MAX1174
CLOCK CS R/C
EOC
Pin Configuration
TOP VIEW
D4/D12 1 D5/D13 2 D6/0 3 D7/0 4 R/C 5 EOC 6 AVDD 7 AGND 8 AIN 9 AGND 10 20 D3/D11 19 D2/D10 18 D1/D9 17 D0/D8
Ordering Information (continued)
PART MAX1158ACUP MAX1158BCUP MAX1158AEUP MAX1158BEUP MAX1174ACUP MAX1174BCUP MAX1174AEUP MAX1174BEUP TEMP RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C 0C to +70C -40C to +85C -40C to +85C PINPACKAGE 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP INPUT VOLTAGE RANGE 10V 10V 10V 10V 5V 5V 5V 5V
MAX1156 MAX1158 MAX1174
16 DVDD 15 DGND 14 CS 13 HBEN 12 REF 11 REFADJ
TSSOP
Chip Information
TRANSISTOR COUNT: 15,383 PROCESS: BiCMOS
14
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14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1156/MAX1158/MAX1174
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
TSSOP4.40mm.EPS

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